Educational Background

• 2015-2019: PhD in ECE (Panjab University Chandigarh India )
• 2007-2009: M.Tech in VLSI Design & Automation Techniques (National Institute of Technology, Hamirpur, H.P, India)
• 2000-2004: B.Tech in ECE (JNTU, Kakinada, A.P, India )

Positions Held

• 2011 to date : Project Engineer-II IN C-DAC, Moahli, India
• 2009 - 2011: Asst. Professor, Chitakara University, Baddi, H.P, India
• 2006-2007: Training Coordinator in CSS, Moahli, India
• 2004-2006: Asst. Professor in GIET, Rajahmundry, A.P, India

Research Interest

• Low Power VLSI Circuit Design
• Nanoscale Interconnect Design & CNT Based Applications
• Regular standard cell library design
• Semiconductor Device Modeling
• Processor Architecture Design

Current Academic Activities

• Teaching the following M.Tech subjects:
  1. Design of Analog and Mixed mode VLSI Circuit Design
  2. Advanced Digital Systems Design
  3. Advanced Digital Signal Processing
  4. Advanced Computer Architecture
• Handling the following Labs:
  1. Advanced Digital Systems Design LAB
  2. Advanced Digital Signal Processing LAB
• Guiding M.Tech theses in VLSI and Embedded fields.
• Conducting Summer Training on “VLSI Design & FPGA Implementation”.
• Teaching ADSP and FPGA modules in Industrial Training on “Diploma in Embedded System Design”.

Academic Awards and Other Achievements

• Recipient of GATE Scholarship during M.Tech.
• Received Certificate of Appreciation for the excellent academic contribution at Chitkara University, Baddi in the year of 2010.
• Certified faculty in VLSI Design from Synopsys University Program.
• Second Topper in M.Tech (VLSI Design and Automation Techniques),
• Topper at mandal level in 10th Class.

Contribution in Projects

• Conceptualized, proposed and executed a core funded project on “CMOS Standard Cell Library Design at 180nm Technology”
• Member in pan CDAC project on “India Microprocessor Design”

Conferences and Workshops

• Organizing member for a Advanced Faculty Training Program on “VLSI Design and Embedded System”, at C_DAC, Mohali from 17th -29th June, 2013.
• Organizing member for “A Workshop on Research Methodologies”, at C-DAC, Mohali from 20th to 21st September, 2013.

Selected Publications

1. Kanika Garg., V.Sulochana., “Low Power Design Analysis of PLL Components in Submicron Technology” Advances in Intelligent Systems and Computing, Vol. 178, 2013, pp 687-696, July 13-15, 2012.
2. Shikha Singh., V.Sulochana., “Reduction of Crosstalk Noise and Delay in VLSI Interconnects Using Schmitt Trigger as a Buffer and Wire Sizing” Advances in Intelligent Systems and Computing, Vol. 178, pp 677-686, July 13-15, 2012.
3. Simrandeep kaur, V.Sulochana Verma, “HDL Implementation of Data Compression: LZW Algorithm”, International Journal Of Advanced Technology & Engineering Research, Volume 2, Issue-2, March 2012,pp.115-120.
4. Ajay Kumar, V.Sulochana Verma “Simulative investigations of DDR2 (SDRAM) Model in HDL” , International Journal Of Advanced Technology & Engineering Research, Volume 2, Issue-2, March 2012,pp. 150-156.
5. Daman Narang., Vemu Sulochana., “Crosstalk Minimization for Coupled RLC Interconnects Using Bidirectional Buffer and Shield Insertion ” , International Journal of VLSI design & Communication Systems (VLSICS), Vol:4, Issue:3, pp. 31-42, June 2013.
6. Shwetambhri Kaushal., Vemu Sulochana., “Delay Minimization in Multi Level Balanced Interconnect Tree” , International Journal of Computer Application, Volume 72– No.11, May 2013 Pp: 7-11 , June 2013.
7. Anurag., Gurmohan Singh., Vemu Sulochana., “ Low Power Dual Edge Triggered Static D Flip-Flop” , International Journal Of Vlsi Design & Communication Systems (VLSICS), vol:4, issue:3, pp. 23-29, june 2013.
8. Gagandeep Singh, Gurmohan Singh, V. Sulochana, “High Performance Low Power Dual Edge – Triggered Static D Flip-Flop,” 4th IEEE Conference on Computing, Communication & Networking Technologies (ICCCNT-2013) at Vivekanandha College of Engineering for Women, Tiruchengode, 4th-6th July 2013.
9. Sidhant kukrety., Gurmohan Singh., Vemu Sulochana., “A Low Power 32 bit CMOS Rom Using a novel ATD Circuit”, International Journal of Electrical and Computer Engineering , Vol.3, Issue:4, pp 509-515, Aug-2013.
10. Shanky Goel, Vemu Sulochana., “Low Leakage Multi Threshold Level Shifter Design using Sleepy Keeper” , International Journal of Computer Application , Vol:72 no. 22 , Pp: 1 – 6 , june 2013.
11. Sunny Anand., Vemu Sulochana., “Design a Low Power ADC for Blood-Glucose Monitoring” , International Journal of Computer Application, Volume:72 Number 14 Pp: 29 – 33 May 2013
12. Kushwant Jain., Vemu Sulochana., “Design and Development of Smart Robot Car for Border Security” , International Journal of Computer Applications, vol. 76, issue 7, pp. 23-29, 2013.